Wednesday, July 14, 2010

Moore Machine

The following state diagram (Fig. 1) describes a finite state machine with one input X and one output Z. The FSM asserts its output Z when it recognizes the following input bit sequence: "1011". The machine will keep checking for the proper bit sequence and does not reset to the initial state after it has recognized the string. As an example the input string X= "..1011011..." will cause the output to go high twice: Z = "..0001001.." . The output will asserts only when it is in state S4 (after having seen the sequence 1011). The FSM is thus a Moore machine.

Figure 1: State diagram, describing the sequence detector implemented as a Moore machine. The number in italics underneath the states indicate which part of the sequence the state remembers.

This state diagram can be described in ABEL code given in Listing 1. The output is described after the STATE Si: statement.

Listing 1: ABEL source code for the Moore machine implementation of the sequence detector described in Fig. 1

module Seqdet2

Title 'Sequence detector implemented as Moore machine'

Declarations

"input and output signals

X, CLOCK, RST PIN;
Z PIN istype 'com';
Q2, Q1, Q0 PIN istype 'reg';

"State register declarations

SREG = [Q2,Q1,Q0];
S0 = [0,0,0];
S1 = [0,0,1];
S2 = [0,1,0];
S3 = [0,1,1];
S4 = [1,0,0];

Equations
"Definition of the state machine clock signal

[Q2,Q1,Q0].AR = RST;
[Q2,Q1,Q0].CLK = CLOCK;

"Define state diagram
STATE_DIAGRAM SREG

STATE S0: Z=0;

IF X THEN S1 ELSE S0;

STATE S1: Z=0;

IF X THEN S1 ELSE S2;

STATE S2: Z=0;

IF X THEN S3 ELSE S0;

STATE S3: Z=0;

IF X THEN S4 ELSE S2;

STATE S4: Z=1;

IF X THEN S1 ELSE S2;

end Seqdet2

The corresponding simulation is shown in Figure 2.

Figure 2: Simulation of the sequence detector (for "1011") described with the state diagram of Fig. 1. (Screen clip from Xilinx XACTstep(TM) Foundation software)

Mealy machine

The following state diagram (Fig. 1) describes a finite state machine with one input X and one output Z. The FSM asserts its output Z when it recognizes the following input bit sequence: "1011". The machine will keep checking for the proper bit sequence and does not reset to the initial state after it has recognized the string. As an example the input string X= "..1011011..." will cause the output to go high twice: Z = "..0001001.." . When the machine is in the state S3 the output will go high after the arrival of a "1" at the input. Thus the output is associated with the transitions as indicated on the state diagram.

Figure 1: State diagram, describing the sequence detector implemented as a Mealy machine.
The number in italics underneath the states indicate which part of the sequence the state remembers.

This state diagram can be described in ABEL code given in Listing 1. The output is described with the "With" keyword to indicate that the output will change when the input goes to one.

Listing 1: ABEL source code for the Mealy Machine implementation of the sequence detector described in Fig. 1

module Seqdet1

Title 'Sequence Detector 1011 with Mealy Machine'

Declarations
"Input and output signals

X, CLOCK, RST PIN;
Z PIN istype 'com';
Q1, Q0 PIN istype 'reg';

"State register definitions
" and assignments of state values

SREG = [Q1,Q0];
S0 = [0,0];
S1 = [0,1];
S2 = [1,0];
S3 = [1,1];

Equations
"Define the clock signal for the state machine

[Q1,Q0].AR = RST;
[Q1,Q0].CLK =CLOCK;

"Define state diagram

STATE_DIAGRAM SREG

STATE S0: IF X THEN S1 ELSE S0;
STATE S1: IF X THEN S1 ELSE S2;
STATE S2: IF X THEN S3 ELSE S0;
STATE S3: IF X THEN S1 WITH Z=1; ELSE S2;

end Seqdet1

The ouput is specified with the "With" keyword. The corresponding simulation is shown in Figure 2.

Figure 2: Simulation of the sequence detector for "1011" described with the state diagram of Fig. 1.
(Screen clip from Xilinx XACTstep(TM) Foundation software)

Notice that the output Z asserts as soon as the input is "1" when in state S3. Comparing this output with the one obtained for a Moore machine of the same sequence detector may let a casual observer think that there is a timing problem as the output seems to asserts already after the "101" input sequence. However, when one looks at the output carefully one concludes that the waveform is correct. One has to realize that the outputs are valid at the end of the state time (just before the positive clock-edge) while the valid inputs are sampled just before the positive clock edge as indicated in Figure 3 below. The input sequence "1011" gives indeed an output sequence of "0001".

Figure 3: Output waveform of the Mealy machine (sequence detector for "1011") with valid inputs and outputs indicated.
(Screen clip from Xilinx XACTstep(TM) Foundation software)

One notices that there is a glitch in the output after the input sequence 10111010. However this occurs at a moment that the output is not valid (the output is valid just before the positive clock edge). The valid output sequence is than 000100000 as expected.

Tuesday, February 23, 2010

AMPLIFIER COUPLING

Earlier in this module it was stated that almost every electronic device contains at least one stage of amplification. Many devices contain several stages of amplification and therefore several amplifiers. Stages of amplification are added when a single stage will not provide the required amount of amplification. For example, if a single stage of amplification will provide a maximum gain of 100 and the desired gain from the device is 1000, two stages of amplification will be required. The two stages might have gains of 10 and 100, 20 and 50, or 25 and 40. (The overall gain is the product of the individual stages-10 X 100 = 20 X 50 = 25 X 40 = 1000.)

Figure 1-8 shows the effect of adding stages of amplification. As stages of amplification are added, the signal increases and the final output (from the speaker) is increased.

Figure 1-8. - Adding stages of amplification.

Whether an amplifier is one of a series in a device or a single stage connected between two other devices (top view, figure 1-8), there must be some way for the signal to enter and leave the amplifier. The process of transferring energy between circuits is known as COUPLING. There are various ways of coupling signals into and out of amplifier circuits. The following is a description of some of the more common methods of amplifier coupling.

Direct Coupling

The method of coupling that uses the least number of circuit elements and that is, perhaps, the easiest to understand is direct coupling. In direct coupling the output of one stage is connected directly to the input of the following stage. Figure 1-9 shows two direct-coupled transistor amplifiers.

Figure 1-9. - Direct-coupled transistor amplifiers.

Notice that the output (collector) of Q1 is connected directly to the input (base) of Q2. The network of R4, R5, and R6 is a voltage divider used to provide the bias and operating voltages for Q1 and Q2. The entire circuit provides two stages of amplification.

Direct coupling provides a good Frequency response since no frequency-sensitive components (inductors and capacitors) are used. The Frequency response of a circuit using direct coupling is affected only by the amplifying device itself.

Direct coupling has several disadvantages, however. The major problem is the power supply requirements for direct-coupled amplifiers. Each succeeding stage requires a higher voltage. The load and voltage divider resistors use a large amount of power and the biasing can become very complicated. In addition, it is difficult to match the impedance from stage to stage with direct coupling. (Impedance matching is covered a little later in this chapter.)

The direct-coupled amplifier is not very efficient and the losses increase as the number of stages increase. Because of the disadvantages, direct coupling is not used very often.

RC Coupling

The most commonly used coupling in amplifiers is RC coupling. An RC-coupling network is shown in figure 1-10.

Figure 1-10. - RC-coupled transistor amplifier.

The network of R1, R2, and C1 enclosed in the dashed lines of the figure is the coupling network. You may notice that the circuitry for Q1 and Q2 is incomplete. That is intentional so that you can concentrate on the coupling network.

R1 acts as a load resistor for Q1 (the first stage) and develops the output signal of that stage. Do you remember how a capacitor reacts to ac and dc? The capacitor, C1, "blocks" the dc of Q1's collector, but "passes" the ac output signal. R2 develops this passed, or coupled, signal as the input signal to Q2 (the second stage). This arrangement allows the coupling of the signal while it isolates the biasing of each stage.

This solves many of the problems associated with direct coupling.

RC coupling does have a few disadvantages. The resistors use dc power and so the amplifier has low efficiency. The capacitor tends to limit the low-Frequency response of the amplifier and the amplifying device itself limits the high-Frequency response. For audio amplifiers this is usually not a problem; techniques for overcoming these frequency limitations will be covered later in this module.

Before you move on to the next type of coupling, consider the capacitor in the RC coupling. You probably remember that capacitive reactance (X_C) is determined by the following formula:

This explains why the low frequencies are limited by the capacitor. As frequency decreases, X_C increases. This causes more of the signal to be "lost" in the capacitor.

The formula for X_C also shows that the value of capacitance (C) should be relatively high so that capacitive reactance (X_C) can be kept as low as possible. So, when a capacitor is used as a coupling element, the capacitance should be relatively high so that it will couple the entire signal well and not reduce or distort the signal.

Impedance Coupling

Impedance coupling is very similar to RC coupling. The difference is the use of an impedance device (a coil) to replace the load resistor of the first stage.

Figure 1-11 shows an impedance-coupling network between two stages of amplification. L1 is the load for Q1 and develops the output signal of the first stage. Since the d.c. resistance of a coil is low, the efficiency of the amplifier stage is increased. The amount of signal developed in the output of the stage depends on the inductive reactance of L1. Remember the formula for inductive reactance:

Figure 1-11. - Impedance-coupled transistor amplifier.

The formula shows that for inductive reactance to be large, either inductance or frequency or both must be high. Therefore, load inductors should have relatively large amounts of inductance and are most effective at high frequencies. This explains why impedance coupling is usually not used for audio amplifiers.

The rest of the coupling network (C1 and R1) functions just as their counterparts (C1 and R2) in the RC-coupling network. C1 couples the signal between stages while blocking the d.c. and R1 develops the input signal to the second stage (Q2).

Transformer Coupling

Figure 1-12 shows a transformer-coupling network between two stages of amplification. The transformer action of T1 couples the signal from the first stage to the second stage. In figure 1-12, the primary of T1 acts as the load for the first stage (Q1) and the secondary of T1 acts as the developing impedance for the second stage (Q2). No capacitor is needed because transformer action couples the signal between the primary and secondary of T1.

Figure 1-12. - Transformer-coupled transistor amplifier.

The inductors that make up the primary and secondary of the transformer have very little dc resistance, so the efficiency of the amplifiers is very high. Transformer coupling is very often used for the final output (between the final amplifier stage and the output device) because of the impedance-matching qualities of the transformer. The Frequency response of transformer-coupled amplifiers is limited by the inductive reactance of the transformer just as it was limited in impedance coupling.

Saturday, February 20, 2010

demorgan's law in boolean algebra

The most obvious way to simplify Boolean expressions is to manipulate them in the same way as normal algebraic expressions are manipulated. With regards to logic relations in digital forms, a set of rules for symbolic manipulation is needed in order to solve for the unknowns.
A set of rules formulated by the English mathematician George Boole describe certain propositions whose outcome would be either true or false. With regard to digital logic, these rules are used to describe circuits whose state can be either, 1 (true) or 0 (false). In order to fully understand this, the relation between the AND gate, OR gate and NOT gate operations should be appreciated. A number of rules can be derived from these relations as Table 1 demonstrates.

P1: X = 0 or X = 1
P2: 0 . 0 = 0
P3: 1 + 1 = 1
P4: 0 + 0 = 0
P5: 1 . 1 = 1
P6: 1 . 0 = 0 . 1 = 0
P7: 1 + 0 = 0 + 1 = 1

Table 1: Boolean Postulates

Laws of Boolean Algebra

Table shows the basic Boolean laws. Note that every law has two expressions, (a) and (b). This is known as duality. These are obtained by changing every AND(.) to OR(+), every OR(+) to AND(.) and all 1's to 0's and vice-versa.
It has become conventional to drop the . (AND symbol) i.e. A.B is written as AB.

T1 : Commutative Law: (a) A + B = B + A
(b) A B = B A
T2 : Associate Law: (a) (A + B) + C = A + (B + C)
(b) (A B) C = A (B C)
T3 : Distributive Law: (a) A (B + C) = A B + A C
(b) A + (B C) = (A + B) (A + C)
T4 : Identity Law: (a) A + A = A
(b) A A = A
T5 :: (a)
(b)
T6 : Redundance Law: (a) A + A B = A
(b) A (A + B) = A
T7 :: (a) 0 + A = A
(b) 0 A = 0
T8 :: (a) 1 + A = 1
(b) 1 A = A
T9 :: (a)
(b)
T10 :: (a)
(b)
T11 : De Morgan's Theorem: (a)
(b)